The present invention relates to a phase-locked loop (PLL) incorporated microcomputer provided with a circuit which detects an interruption of an oscillation of an external oscillator, as a clock source of the microcomputer, which is externally connected to the microcomputer.
In a microcomputer system employed in a machine such as automobile that is responsible for human life, the concept of fail-safe is an important point as well as high reliability. The fail-safe is directed for detecting an abnormality when a portion of a system is in an abnormal state, and conducting switching to appreciate an auxiliary unit. One example of such abnormal states is an interruption of oscillation of an external oscillator of a microcomputer. The interruption of oscillation of the external oscillator occurs due to an open, short-circuit, or the like of the external oscillator.
A mechanism as follows is mounted on a Microcomputer M16C/6N group or the like manufactured by MITSUBISHI ELECTRIC CORPORATION. The mechanism is such that when an interruption of oscillation of the external oscillator occurs, the microcomputer detects the interruption and an internal clock is switched from a connection terminal of the external oscillator to an internal oscillator such as an internal ring oscillator.
FIG. 5 is a configuration diagram of a conventional oscillation stop detector. The oscillation stop detector is incorporated in a chip of a microcomputer. A clock edge detector 100 detects an edge of an externally generated clock signal XIN input from a connection terminal of an external oscillator, and generates a charge/discharge control pulse signal in response to the detection. A charger/discharger 101 performs an operation which gradually charges a charger having an RC time constant, and an operation which discharges according to the charge/discharge control pulse signal. When the externally generated clock signal XIN is normally oscillated, discharging according to the charge/discharge control pulse signal is periodically performed before the charging is completed. However, when the externally generated clock signal XIN is interrupted, the charge/discharge control pulse signal is not also generated. Therefore, discharging is not performed in the charger/discharger 101 and thereby charging is completed. The charger/discharger 101 detects the completion of the charging as an interruption of oscillation of the external oscillator, and generates an oscillation-stop interruption signal or the like in response to the detection.
Further, a switching section 103 switches a main clock of the microcomputer from the externally generated clock signal XIN to an oscillation signal of an internal ring oscillator 102 based on the oscillation-stop interruption signal, which enables the microcomputer to operate even after the externally generated clock signal XIN is interrupted. Therefore, it becomes possible to perform a necessary fail-safe processing.
The charger/discharger 101 used in the conventional oscillation stop detector is configured with a resistor R and a capacitor C. Particularly the capacitor C occupies a large area in terms of the layout, which prevents an area of a chip from being reduced. Further, the ring oscillator circuit serving as an internally generated clock oscillation source, which is used only when an interruption of oscillation is detected, is required excessively. The time constant of the RC is largely varied due to changes of a manufacturing process or a usage condition of a semiconductor, and it is thereby necessary to carefully perform tuning in terms of the layout in order to detect an accurate interruption of oscillation, which may lead to mistakes of the layout.
On the other hand, some one-chip microcomputers are of PLL incorporated type. In the PLL incorporated one-chip microcomputer, a clock signal from the external oscillator or an internal reference oscillator is input to the PLL circuit. The PLL circuit comprises a phase comparator, a charge pump, a voltage-controlled oscillator (VCO), and a frequency divider. The PLL circuit performs a phase synchronization of the input clock signal and an internally generated clock signal, generates a fast clock signal by multiplying the phase-synchronized clock signal by n, and outputs the fast clock signal as an internal clock signal used in the microcomputer.
The conventional PLL incorporated one-chip microcomputer is internally provided with another clock signal generator in order to cope with an abnormality of an externally generated clock signal from the external oscillator, so that switching is performed from an internal clock signal output from the PLL circuit to a clock signal from another internal clock signal generator, when the externally generated clock signal is, abnormal.
In the conventional art, however, it is necessary to internally provide another clock signal generator which is used only when the external oscillator detects an interruption of oscillation, which results in increase of the number of circuit configurations.
As described above, according to the oscillation stop detector based on the former conventional art, there is a problem that the RC time constant is largely varied due to manufacturing process or usage condition of a semiconductor. Further, there is a problem that the layout area is increased in order to secure a large RC time constant and incorporate a dedicated internally generated clock oscillation source.
Further, according to the PLL-incorporated one-chip microcomputer based on the latter conventional art, it is necessary to internally provide another clock signal generator which is used only when an interruption of oscillation of the external oscillator is detected, which results in upsizing of the circuit configuration and increase in the occupied circuit area, thereby preventing an area of a chip from being reduced.
It is an object of this invention to provide a phase-locked loop (PLL) incorporated microcomputer capable of accurately detecting an interruption of oscillation of the external oscillator, and capable of forming an oscillation stop detector for the external oscillator with a simple configuration and a small occupied circuit area.
The PLL incorporated microcomputer according to this invention comprises an edge detector, a PLL circuit, a counter, and an externally generated clock signal stop detector. More specifically, the edge detector detects an edge of an input externally generated clock signal and generates an edge detection signal. The PLL circuit generates a clock signal, phase-synchronizes the clock signal with the externally generated clock signal and generates a phase-synchronized signal, and multiplies the phase-synchronized signal by n to output the multiplied signal as an internal clock signal used in the microcomputer. The counter is cleared when the edge detector outputs the edge detection signal, performs a count operation using an internal clock signal output from the PLL circuit as a count source, and outputs a count value. The externally generated clock signal stop detector detects that the externally generated clock signal is interrupted when the count value of the counter has exceeded a predetermined set value, and outputs an external clock stop detection signal.
This invention is based on the feature such that a PLL circuit continues oscillation with a particular low frequency by an incorporated voltage-controlled oscillator (VCO) even when a clock signal to be input is interrupted.
According to the above aspect, the internal clock signal output from such a PLL circuit becomes a signal n times the externally generated clock signal when the externally generated clock signal is normal, and the signal becomes a signal with a particular low frequency when the externally generated clock signal is abnormal.
Other objects and features of this invention will become apparent from the following description with reference to the accompanying drawings.